In most integrated circuit memory devices, each storage cell is individually accessed using a unique access address. However, in some integrated circuit memory devices, several other storage cells are accessed simultaneously and the contents thereof are held temporarily in a buffer. Typically, the access addresses of these "extra" storage cells differ from the original access address by only one or two bits. However, subsequent accesses to these cells can be accomplished by simply executing additional access cycles without changing the access address. In the art, such memories are referred to as "nibble mode". In some other integrated circuit memories, a portion of the original access address can be "assumed" for one (or more) subsequent accesses, so that only the least significant portion of the address needs to be decoded, etc. Thus, once the original access has been completed, subsequent accesses to "related" storage cells will be significantly quicker. These types of memories are sometimes referred to as "column mode" or "static column". In memory systems constructed using such enhanced performance memory devices, the effect is to allow the memory to sustain rapid transfers of several operands in "bursts" of m, where m is two (2) to the n power, n being an integer and characteristic of the selected memory device.
In systems having caches, this burst mode of operation facilitates fast filling of entire cache lines. However, the burst operation should only be initiated if all of the entries in the cache line are invalid. Similarly, a burst operation should not be initiated if further data processing must be delayed in order to cache the nonessential entries in a cache line.